1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to a semiconductor read-only memory (ROM) device of the type including a plurality of diode-type memory cells and a method for fabricating the same. It is a distinctive feature of this invention that the bit lines for the ROM device are formed in an alternate manner on the bottom of a plurality of substantially parallel-spaced trenches and on the top of the solid portions between these trenches such that the packing density of the memory cells on the ROM device can be increased.
2. Description of Related Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that are repeatedly used, such as the BIOS (abbreviation for Basic Input/Output System, a widely used operating system on personal computers) or the like. The manufacture of ROMs involves very complicated and time-consuming processes and requires costly equipment and material to achieve. Therefore, the information to be stored in ROMs is usually first defined by the customer and then furnished to the factory to be programmed into the ROMs.
The feature size of ROMs is dependent on the semiconductor fabrication technology. Conventional ROMs are formed by an array of MOSFETs (metal-oxide semiconductor field-effect transistor), each MOSFET being associated with one single memory cell of the ROM device. The binary data stored in each of these MOSFET-based memory cell is dependent on a particular electrical characteristic thereof, such as the threshold voltage.
If the channel of a MOSFET memory cell is doped with a high concentration of an impurity material, this MOSFET will be set to a low threshold voltage that is less than the gate voltage, effectively setting this MOSFET memory cell to a permanently-ON state representing the permanent storage of a first binary digit, for example 0.
On the other hand, if the channel of a MOSFET memory cell is not doped with impurities, the MOSFET memory cell will have a high threshold voltage that is greater than the gate voltage, thus effectively setting the MOSFET memory cell to a permanently-OFF state representing the permanent storage of a second binary digit, for example 1. This type of ROM device will be described in more detail in the following with reference to FIGS. 1A through 1C.
Referring to FIG. 1A, there is shown a schematic top view of a conventional ROM device. This ROM device is formed with a plurality of substantially parallel-spaced diffusion regions which serve as a plurality of buried bit lines 12a, 12b, 12c beneath a plurality of field oxide layers 200. Further, a plurality of word lines (WL1, WL2) 18, 18' are formed in such a manner as to intercross the bit lines 12a, 12b, 12c at a right angle. The intersections between the bit lines 12a, 12b, 12c and the word lines WL1, WL2 are the locations where the memory cells of the ROM device are formed. For instance, a first memory cell 16a is formed on the word line WL2 between the bit lines 12a, 12b; a second memory cell 16b is formed on the word line WL2 between the bit lines 12b, 12c; a third memory cell 16c is formed on the word line WL1 between the bit lines 12a, 12b; and a fourth memory cell 16d is formed on the word line WL1 between the bit lines 12b, 12c. The binary data that are permanently stored in these memory cells 16a, 16b, 16c, 16d are dependent on the concentration of the associated diffusion regions. For instance, the N.sup.+ regions in FIG. 1 represent that the associated memory cells 16a, 16d are set to a permanently-ON state; while the memory cells 16b, 16c are set to an permanently-OFF state.
FIG. 1B is a perspective view of a cutaway part of the ROM device of FIG. 1A, with the front side thereof showing a cross-sectional view cutting through the line II--II in FIG. 1 This perspective diagrams shows that the ROM device includes a P-type silicon substrate 10 on which the bit lines 12a, 12b, 12c and the overlaying field oxide layers 200 are formed. Beside these, the ROM device includes a thin insulating layer 14 on which the word lines (WL1, WL2) 18, 18' are formed.
FIG. 1C is an equivalent circuit diagram of the ROM device of FIG. 1A. This circuit diagram shows that the two word lines WL1 and WL2 are used to access the binary data stored in the four memory cells 16a, 16b, 16c, 16d via the three bit lines (BL1, BL2, BL3) 12a, 12b, 12c. In this example, the first memory cell 16a is set to a permanently-ON state; the second memory cell 16b is set to a permanently-OFF state; the third memory cell 16c is set to a permanently-OFF state; and the fourth memory cell 16d is set to a permanently-ON state.
One drawback to the foregoing ROM device is that the MOSFET-based memory cells are comparatively large in size and thus require a large space in the wafer to construct. When the feature size of these MOSFET-based memory cells is further reduced, the so-called short-channel effect will occur, causing a leakage current in the ROM device. Moreover, the operating voltage of the foregoing ROM device is restricted by the threshold voltage of the MOSFET-based memory cells. If the operating voltage is low, the current in the bit lines will be also low, causing the sense amplifiers difficulty in distinguishing whether the accessed data is 0 or 1.